An image data handling apparatus, such as a facsimile machine, effects lower area highlighting, in which image data are highlighted more in an area where a density of an image is lower (or the image gets darker) as shown in FIG. 8, so that input image data are corrected in a more realistic manner as previously mentioned.
A typical level correcting technique in the prior art uses a memory as is disclosed in, for example, Japanese Laid-Open Patent Application No. 308532/1993 (Tokukaihei 5-308532). To be more specific, let an address of input image data be x, and let the output image data from the address x be Y, then non-linear characteristics as shown in FIG. 8 is are given to the data stored in the memory.
Accordingly, as shown in FIG. 9, the output data are shifted with respect to a memory address, and as set forth in Table 1 below, the data take a value shifted to a higher order with respect to an input address. Thus, even when the output image data have non-linear characteristics with respect to the input image data, the output data from the memory can be used as corrected data by pre-storing the output image data at a memory address for the input image data x.
TABLE 1 ______________________________________ ADDRESS 0 1 2 3 . . . 253 254 255 DATA 4 8 12 16 . . . 252 252 252 ______________________________________
In above-mentioned Japanese Laid-Open Patent Application No. 308532/1993, when an image having both a picture area and a text area is formed, an original is read to compute a density distribution first. Thereafter, a .gamma. table made of corrected value data in accordance with the density distribution is created, after which the original is read again to output a formed image.
However, since the number of levels and a memory capacity are directly proportional, the above conventional technique has a problem that a memory capacity increases significantly if the number of the levels increases.
For example, in the case of 2.sup.6 =64-level correction, where each pixel is corrected with 6-bit accuracy when a unit image data is 6-bit long, a memory capacity of 6.times.(2.sup.6-1)=378 bits is necessary.
If each memory element is made of a gate array, each flip-flop demands seven NAND gates in NAND conversion generally, and in total, as many as 378.times.7=2646 gates are necessary.
Thus, the prior art has a problem in that a circuit is upsized considerably if the number of levels increases.